The present invention relates to a method of manufacturing semiconductor devices having high reliability, and to the resulting devices. The present invention has particular applicability in manufacturing highly miniaturized non-volatile semiconductor devices with reduced device leakage.
Various issues arise in attempting to satisfy the ever increasing demands for miniaturization, particularly in fabricating non-volatile semiconductor devices, such as flash memory devices, e.g., electrically erasable programmable read only memory (EEPROM) devices. The demands for continuing miniaturization have led to the fabrication of flash memory devices comprising transistors having a gate width of about 0.18 micron and under and gate structures spaced apart by a small gap of about 0.33 micron or less. In accordance with conventional practices, an oxide sidewall spacer is formed on side surfaces of the gate stack and a conformal silicon nitride layer, serving as an etch stop layer, is deposited over the gate structures including the sidewall spacers, thereby further reducing the gap between gate structures to about 0.25 micron or less. In accordance with conventional practices, a first interlayer dielectric (ILD0) is deposited over the gate structures and fills the gaps therebetween. Gap filling is then implemented followed by rapid thermal annealing, as at a temperature of about 820xc2x0 C. for about 120 seconds.
As the distance between sidewall spacers of neighboring gate structures, after depositing the etch stop layer decreases to below about 0.125 micron, it becomes extremely difficult to fill the gaps with a gap fill oxide, even after post deposition rapid thermal annealing, without void formation. Such voiding in ILD0 can lead to an open contact and shorting between contacts, thereby causing leakage and low production yields.
As miniaturization of flash technology proceeds apace, additional problems are encountered with respect to ILD0 integrity as the aspect ratio of the gate stacks increases to about 3.0 and higher. It was found that undercutting of the sidewall spacers occurs, and even extends into the substrate surface. It is believed that such undercutting stems in part from undercutting of the oxide liner during wet cleaning with diluted hydrofluoric acid, such as hydrofluoric acid diluted with water at a level of 10:0 to 300:1, prior to metal deposition in implementing salicide technology. In addition, after silicidation, etching is conducted to remove unreacted metal remaining on the sidewall spacers, thereby attacking the silicon under the spacers, exacerbating the undercut regions. Attempts to deposit a phosphorous (P)-doped high density plasma (P-HDP) oxide layer as a gap fill layer have not been successful in filling these undercut regions, as such P-HDP oxide layers do not have sufficient fluidity. Consequently, the undercut regions remain as voids, thereby adversely impacting device reliability, as by facilitating boron penetration from the gate electrode through the gate oxide into the substrate, resulting in leakage upon rapid thermal annealing, as at a temperature of about 840xc2x0 C. for about three minutes, during densification.
Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices, particularly flash memory devices, such as EEPROMs, with improved reliability. There exists a particular need for methodology enabling the fabrication of flash memory devices, such EEPROMs, with no or significantly reduced voids in the ILD0 by enabling gap filling between neighboring transistors such that the undercut regions in sidewall spacers are filled.
An advantage of the present invention is a method of manufacturing a semiconductor device exhibiting improved reliability.
Another advantage of the present invention is a method of manufacturing a flash memory semiconductor device with improved reliability.
A further advantage of the present invention is a method of manufacturing a flash memory device with reduced voids in the ILD0 between closely spaced apart transistors and filled in undercut regions in sidewall spacers.
Another advantage of the present invention is a reliable semiconductor device having reduced leakage by virtue of oxide filled undercut regions in dielectric sidewall spacers on side surfaces gate electrodes.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming two gate electrode structures with a gap therebetween on a semiconductor substrate; forming dielectric sidewall spacers on side surfaces of the gate electrode structures with undercut regions at the substrate; and depositing a boron (B)-doped high density plasma (B-HDP) or a B and phosphorus (P)-doped high density plasma (BP-HDP) oxide film to fill the gap, the B-HDP or BP-HDP oxide film having sufficient fluidity to flow into the undercut regions.
Embodiments of the present invention comprise forming flash memory gate stacks with silicon oxide spacers having undercut regions at the semiconductor substrate, forming a conformal etch stop layer thereon, such as silicon nitride, and then depositing a B-HDP or BP-HDP oxide film containing 4.0 to 6.0 wt. % B or containing 4.0 to 6.0 wt. % B and 4.0 to 6.0 wt. % phosphorus (P) filling the gap. Heating is conducted during and after deposition to cause the B-HDP or BP-HDP oxide film to flow into and fill the undercut regions. Embodiments of the present invention include heating at a temperature of 550xc2x0 C. to 750xc2x0 C. during deposition and at a temperature of 700xc2x0 C. to 1,000xc2x0 C. after deposition to complete reflowing of the B-HDP or BP-HDP oxide into and filling the undercut regions and to densify the oxide film.
Another advantage of the present invention is a semiconductor device comprising: two gate electrode structures, spaced apart by a gap, on a semiconductor substrate; dielectric sidewall spacers on side surfaces of the gate electrode structures; the dielectric sidewall spacers having undercut regions at the substrate, and a boron (B)-doped high density plasma (B-HDP) or a B and phosphorus (P)-doped high density plasma (BP-HDP) oxide film filling the gap between the gate electrode structures and filling the undercut regions.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description wherein embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.